1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and a resulting semiconductor device, and more particularly to a method of manufacturing a semiconductor device called a chip scale package or a chip size package (CSP).
2. Description of the Related Art
In recent years, the reduction in size and weight of electronic appliances, such as mobile phones, mobile computers, personal digital assistants (PDAs), home video cameras, and digital cameras, and peripherals of these electronic appliances has been rapidly accomplished. According to such market trend, there is a high necessity for reducing the size, thickness and weight of a semiconductor chip used in the electronic appliances and for mounting the semiconductor chip on a micro wire board at high density. In order to satisfy such necessities, a chip size semiconductor device or a package size device slightly larger than the chip size semiconductor device, i.e., a so-called a chip scale package or a chip size package (CSP), is under development.
The CSP is advantageous in that the CSP is subminiaturized and thin, and the CSP can be mounted on a printed board using well-known surface mounting technology. Also, the CSP is advantageous in that a semiconductor chip is mounted as a package structure, and therefore it is possible to ensure high-quality mounting, as compared with bare chip mounting technology for directly mounting the semiconductor chip on the printed board.
A CSP and a manufacturing method thereof are disclosed, for example, in Japanese Patent Application Kokai (Laid-Open) No. 2001-156209 and Japanese Patent Application Kokai No. 2004-241696. According to the disclosures of Japanese Patent Application Kokai No. 2001-156209 and Japanese Patent Application Kokai No. 2004-241696, a plurality of protruding electrodes are formed on a dielectric film (insulation film) and wires stacked on a semiconductor substrate, and a conductor layer is formed around the protruding electrodes. It is possible to prevent electromagnetic noise generated in a circuit element forming region from leaking to the outside and to reduce influence of electromagnetic noise from the outside and influence of optical noise from the outside by the provision of the conductor layer.